Latest Event Updates

Verilog Code for Mealy and Moore 1011 Sequence detector

Posted on

Mealy FSM verilog Code


module moore1011
(input clk, rst, inp,
output reg outp);

reg [2:0] state;
parameter S0=0, S1=1, S2=2, S3=3,S4=4;
///next state logic
always @(posedge clk, posedge rst)
if(rst==1)
state<=S0;
else
case(state)

S0: if(inp)
state<=S1;
else
state<=S0;

S1: if(inp)
state<=S1;
else
state<=S2;

S2: if(inp)
state<=S3;
else
state<=S0;

S3: if(inp)
state<=S4;
else
state<=S1;

S4: if(inp)
state<=S0;
else
state<=S2;
endcase

///output logic
always @(state)
case(state)

S0:
outp<=0;
S1:
outp<=0;
S2:
outp<=0;
S3:
outp<=0;
S4:
outp<=1;
endcase
endmodule

Moore FSM Verilog code

module mealy1011(clk,rst,inp,outp);
input clk,rst,inp;
output reg outp;
reg [1:0]state;
parameter S0=0, S1=1, S2=2, S3=3;

always @(posedge clk or posedge rst)
if(rst)
state<=S0;
else
case(state)

S0: if(inp)
state<=S1;
else
state<=S0;
S1: if(inp)
state<=S1;
else
state<=S2;
S2: if(inp)
state<=S3;
else
state<=S0;
S3: if(inp)
state<=S1;
else
state<=S2;
endcase
//
always @(state,inp)

case(state)
S0: if(inp)
outp<=0;
else
outp<=0;
S1: if(inp)
outp<=0;
else
outp<=0;
S2: if(inp)
outp<=0;
else
outp<=0;
S3: if(inp)
outp<=1;
else
outp<=0;
endcase
endmodule

This entry was posted in Uncategorized.